Scrying the AMD GFX1250 LLVM Tea Leaves

(chipsandcheese.com)

58 points | by mfiguiere 15 hours ago

3 comments

  • androiddrew 2 hours ago
    Where does someone start on kernel development for an RDNA4? Books, resources, whatever?

    8 year developer just getting into to AI side of the house

  • majke 3 hours ago
    I'm a heavy user of NVIDIA LOP3 instruction (uint32). I wonder when AMD will finally support it well.
    • Archit3ch 2 hours ago
      I'm very interested in your use case.

      I looked into bit-slicing techniques, but they increase throughput at the cost of massive latency. This is not acceptable for realtime audio.

  • WithinReason 6 hours ago
    ...not just implementing barriers in hardware but also full monitors, allowing the wave to be notified if a specific cache line is evicted from the L2 cache.

    What is this feature for? When do you need it?

    • dragontamer 3 hours ago
      GPUs are absurdly SMT. Like 8 threads or 10 threads (or tracked instruction pointers) per hardware instruction execution unit (for AMD, the Workgroup Processor, WGP)

      I have to imagine that some kind of queue or data structure would benefit from this information. Especially with server GPU tasks staying resident inside of a WGP for literally hours at a time.