Their books are perfect, and I hope this textbook gets adopted by thousands of colleges. Our RISC-V future is bright, now we need one on SoC bringup and getting your OS running on that SoC.
Based on description it doesn't sound like SoC design, it sounds like a book about RISC-V microprocessors. To the untrained eye, that sounds similar, but a microprocessor is one part of an SoC, and sometimes it can be a very small part based off the role the microprocessor plays.
What are some good books/resources on overall System-On-Chip Design?
There is a surprising paucity of material on SoC design which are comprehensive and complete. Application-specific tailored features, Cost, Performance, Area, Power etc. all go into SoC design and yet there does not seem to be a comprehensive resource bringing everything together. Even wikipedia isn't detailed enough - https://en.wikipedia.org/wiki/System_on_a_chip
I know of only two decent books viz. Computer System Design: System-on-Chip by Michael Flynn and Wayne Luk (this is pretty good) and the older ARM System-on-Chip Architecture by Steve Furber.
I like RISC-V (it's been my job for the last 7 years) but this is nonsense. Not everything RISC-V is good. CLIC was awful (thankfully it has been abandoned). The spec is not especially well written - the style is inconsistent due to being written by many authors, and it is waaaay too much of a textbook rather than a proper spec. (There is some ongoing work to improve this tbf.)
There's a practically unending list of undefined/implementation defined behaviours, which is great if you want to implement an ultra minimal microcontroller with 100 flops, but pretty awful otherwise.
Requiring the C (compressed) extension in the RVA profiles was definitely a mistake. The lack of true 16/64kB pages and conditional moves are probably a mistake (though fixable).
I don't know how any of these make it more robust and mature.
(But to be clear, I still think it's pretty good overall.)
Requiring C (compressed) is necessary to avoid splitting the Linux ecosystem. Chips lacking C would never be able to run binaries compiled with C. There's no practical way for such binaries to detect this and work around it at runtime as they can with other extensions. And emulation would be super-slow given a large proportion of instructions are compressed.
Also the excuse given by Qualcomm - that it would make all instructions fixed length and so much easier to decode - is just wrong. RISC-V supports variable length instructions, even much longer than 32 bits, and you've just got to deal with it. Just because Qualcomm acquired a company with a microarchitecture that could only deal with fixed length instructions is no reason to break the ecosystem.
Also interested in the problems you see in Zicond. It claims at least to give you most of the benefit of conditional moves using only two instructions, but I've not actually tried using it. (https://docs.riscv.org/reference/isa/extensions/zicond/_atta...)
> Requiring C (compressed) is necessary to avoid splitting the Linux ecosystem. Chips lacking C would never be able to run binaries compiled with C.
Yes that's precisely the point of excluding it from the RVA profiles. It would mean that Linux distros don't compile code with C enabled, so chips are free to not support C and therefore can achieve higher performance (probably). And it opens 3/4 of the instruction encoding space for use by other things.
> Also the excuse given by Qualcomm - that it would make all instructions fixed length and so much easier to decode - is just wrong. RISC-V supports variable length instructions, even much longer than 32 bits, and you've just got to deal with it.
It's not wrong. RISC-V defines a mechanism by which 48/64 bit instructions might be used, but currently none are actually defined. All existing instructions are 16 or 32 bits. Without C all instructions are 32 bits. You don't have to deal with 48 bit instructions because there aren't any.
It's possible that they will add some in future, but I'm doubtful of that because a) it would be a huge pain, and b) they didn't for Vector which is where it would have been most useful.
> Just because Qualcomm acquired a company with a microarchitecture that could only deal with fixed length instructions is no reason to break the ecosystem.
Yeah it was too late to change but that doesn't mean it wasn't a mistake.
> RISC-V supports variable length instructions, even much longer than 32 bits, and you've just got to deal with it.
...no, not really? There is nothing like 9 byte-long MOVABS instruction of x64 that exists on RISC-V.
The main difficulty in decoding is that 32-bit instructions are not required to be 4-byte aligned, this means that naïve decoders will spend 2 cycles fetching such split instructions. It's possible to add a 4-byte ring buffer but all in all, efficiently supporting the C extension is non-trivial.
RISC-V definitely does support instructions longer than 32 bits, starting at 48 bits (ie. 32 + 16), and going much longer. They are much easier to decode than x86 because the length is evident from the first byte. No ratified extension uses them now, but you're going to need to deal with them as the extension space gets more crowded. Including dealing with instructions split across cache lines and pages, and instructions aligned to 16 bits.
https://peer.asee.org/57147.pdf
Harris and Harris (no relation) have an excellent book on digital design using RISC-V as the domain problem, https://pages.hmc.edu/harris/ddca/ddcarv.html
https://pages.hmc.edu/harris/ddca/
Their books are perfect, and I hope this textbook gets adopted by thousands of colleges. Our RISC-V future is bright, now we need one on SoC bringup and getting your OS running on that SoC.
There is a surprising paucity of material on SoC design which are comprehensive and complete. Application-specific tailored features, Cost, Performance, Area, Power etc. all go into SoC design and yet there does not seem to be a comprehensive resource bringing everything together. Even wikipedia isn't detailed enough - https://en.wikipedia.org/wiki/System_on_a_chip
I know of only two decent books viz. Computer System Design: System-on-Chip by Michael Flynn and Wayne Luk (this is pretty good) and the older ARM System-on-Chip Architecture by Steve Furber.
Full disclosure: I have no affiliation with the author, but I'm sharing because I genuinely believe in the work.
There's a practically unending list of undefined/implementation defined behaviours, which is great if you want to implement an ultra minimal microcontroller with 100 flops, but pretty awful otherwise.
Requiring the C (compressed) extension in the RVA profiles was definitely a mistake. The lack of true 16/64kB pages and conditional moves are probably a mistake (though fixable).
I don't know how any of these make it more robust and mature.
(But to be clear, I still think it's pretty good overall.)
Requiring C (compressed) is necessary to avoid splitting the Linux ecosystem. Chips lacking C would never be able to run binaries compiled with C. There's no practical way for such binaries to detect this and work around it at runtime as they can with other extensions. And emulation would be super-slow given a large proportion of instructions are compressed.
Also the excuse given by Qualcomm - that it would make all instructions fixed length and so much easier to decode - is just wrong. RISC-V supports variable length instructions, even much longer than 32 bits, and you've just got to deal with it. Just because Qualcomm acquired a company with a microarchitecture that could only deal with fixed length instructions is no reason to break the ecosystem.
Also interested in the problems you see in Zicond. It claims at least to give you most of the benefit of conditional moves using only two instructions, but I've not actually tried using it. (https://docs.riscv.org/reference/isa/extensions/zicond/_atta...)
Yes that's precisely the point of excluding it from the RVA profiles. It would mean that Linux distros don't compile code with C enabled, so chips are free to not support C and therefore can achieve higher performance (probably). And it opens 3/4 of the instruction encoding space for use by other things.
> Also the excuse given by Qualcomm - that it would make all instructions fixed length and so much easier to decode - is just wrong. RISC-V supports variable length instructions, even much longer than 32 bits, and you've just got to deal with it.
It's not wrong. RISC-V defines a mechanism by which 48/64 bit instructions might be used, but currently none are actually defined. All existing instructions are 16 or 32 bits. Without C all instructions are 32 bits. You don't have to deal with 48 bit instructions because there aren't any.
It's possible that they will add some in future, but I'm doubtful of that because a) it would be a huge pain, and b) they didn't for Vector which is where it would have been most useful.
> Just because Qualcomm acquired a company with a microarchitecture that could only deal with fixed length instructions is no reason to break the ecosystem.
Yeah it was too late to change but that doesn't mean it wasn't a mistake.
Zicond looks good - I forgot that exists.
...no, not really? There is nothing like 9 byte-long MOVABS instruction of x64 that exists on RISC-V.
The main difficulty in decoding is that 32-bit instructions are not required to be 4-byte aligned, this means that naïve decoders will spend 2 cycles fetching such split instructions. It's possible to add a 4-byte ring buffer but all in all, efficiently supporting the C extension is non-trivial.
I'm not sure what point you're making TBH.